The present invention relates to a semiconductor device and, more particularly, to a method for forming a lower electrode for use in a semiconductor device which is capable of preventing the bottom electrode from misaligning with a storage node contact.
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, several structures for the capacitor have been proposed, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing a three-dimensionally arranged capacitor is a long and tedious one and consequently incurs high manufacturing costs. Therefore, there is a strong demand for a new memory device that can reduce the cell area while securing a requisite volume of information without requiring complex manufacturing steps.
Since capacitance is a function of dielectric area and the dielectric constant of the dielectric material, a high K dielectric, e.g., barium strontium titanate (BST) or the like, has been used as a capacitor thin film in place of conventional silicon oxide film or silicon nitride film to increase the capacitance in a given area. However, the use of materials with a high dielectric constant presents a problem when using a conventional material like ruthenium (Ru) as an electrode in that the Ru electrode creates leakage current in the capacitance device.
To address this problem, platinum (Pt) has been found to be suitable for use in electrodes in this situation. However, if a novel metal such as Pt is applied to a capacitor as a lower electrode, there easily occurs a misalignment problem between a storage node contact and a bottom electrode. On the other hand, if a barrier layer is adopted to prevent the leakage current problem, it is directly in contact with a high K capacitor dielectric, which will, in turn, easily oxidize the barrier layer during the following hot thermal processes.
Thus, there remains a need for a method of forming an electrode compatible with a high K capacitor dielectric which solves the above-described problems.
It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of preventing a bottom electrode incorporated therein from misaligning with a storage node contact.
In accordance with an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising the steps of a) preparing an active matrix provided with at least one diffusion region and an insulating layer formed thereon; b) patterning the insulating layer into a predetermined configuration, thereby exposing the diffusion regions; c) forming metal silicide films on the exposed diffusion regions; d) forming a metal layer on the exposed diffusion regions and the insulating layer; e) patterning the metal layer to a preset configuration, thereby obtaining supporting members on the metal silicide films; f) forming bottom electrodes on the supporting members; and g) forming capacitor dielectrics and top electrodes on the bottom electrodes.